1. Field of the Invention
The present invention relates to digital data transmission, and more particularly to a frequency difference detector for use in a frequency/phase-locked loop clock recovery system.
2. Description of Related Art
Digital signals are widely used in telecommunication systems for transmission of multiplexed pulse code modulated (PCM) voice channels over twisted pair, coaxial cable, or optical fiber media. Digital signals originate with sharply defined transitions and a consistent bit rate, but this well-defined form is eroded by loss, dispersion and noise in the transmission media. Regularly spaced regenerators are used to reconstruct the data stream, however the restored transitions do not generally match the original transition times. The new transitions tend to vary randomly about the nominal transition time. In this context, jitter is defined as abrupt, spurious variations in the phase of successive pulses, as compared with the phase of a continuous oscillator.
A digital signal which contains a binary data signal and a clocking signal in combination is referred to as a return to zero (RZ) signal, whereas a digital signal which contains a binary data signal without a clocking signal is referred to as a non return to zero (NRZ) signal (i.e., simple binary). NRZ signals require only one half the bandwidth of RZ signals, but the receiving unit must include complex circuitry to derive the bit cell timing.
Many such receiving units use phase-locked loop clock recovery systems for synchronizing a local oscillator with the NRZ signal. The phase-locked loop typically includes a phase detector that detects the phase difference between the NRZ signal and a reference signal, a low pass filter that filters an error signal generated by the phase detector, and a voltage controlled oscillator that receives the filtered error signal and generates the reference signal. In this manner, the reference signal "locks" on the frequency of the NRZ signal. A phase-locked loop can lock onto a very small spectral component in a data stream so that long strips of one's or zero's have a negligible effect on timing phase or amplitude. Thus, a phase-locked loop can be used to fill in the missing pulses in a data stream and eliminate jitter.
Conventional phase-locked loops require a design trade-off between stability and capture range. This limitation has been partially overcome by frequency/phase-locked loops which use a frequency-locked loop during an acquisition mode when the capture range is of primary concern. Once the proper frequency is locked, the loop is dominated by a parallel phase-locked loop which provides stability during steady-state operation.
FIG. 1 shows a frequency/phase-locked loop disclosed in Cordell et al., "A 50 Mhz Phase- and Frequency-Locked Loop," IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 6, December 1979, pp. 1003-1010, which is incorporated by reference. The phase-locked loop includes phase detector 12, and the frequency-locked loop includes frequency difference detector 14. The phase-locked loop and frequency-locked loop share low-pass filter 16 and voltage controlled oscillator 18. Phase detector 12 is a Hogge phase detector. Low-pass filter 16 is a conventional lead-lag circuit in which the reactive elements provide a zero frequency and a pole frequency, the gain is constant below the zero frequency and above the pole frequency, and the gain increases between the zero and pole frequencies. Voltage controlled oscillator 18 produces the reference signal as a train of clock pulses, the frequency of which is dependent upon the voltage at its control input.
FIG. 2 shows frequency difference detector 14, which includes parallel in-phase and quadrature branches. The in-phase branch includes phase detector 20, low-pass filter 22 and quantizer 24. The quadrature branch includes 90-degree phase shifter 26, quadrature phase detector 28, low-pass filter 30, quantizer 32 and differentiator 34. A square wave generated by quantizer 24 and alternating polarity pulses generated by the differentiator 34 are multiplied by phase detector 36 to provide slip pulses at the output. The amplitude of the slip pulses corresponds to the frequency difference between the NRZ signal and the reference signal, and the polarity of the slip pulses represents the sign of the frequency difference. For instance, if the NRZ signal has a greater frequency than the reference signal then the slip pulses have positive polarity, and if the NRZ signal has a smaller frequency than the reference signal then the slip pulses have negative polarity.
Frequency difference detector 14 has several disadvantages. For instance, differentiator 34 includes a capacitor and a resistor, and a well-controlled tub resistor is particularly difficult to implement with submicron CMOS processes. Another disadvantage is the low repetition rate of the slip pulses, which corresponds to twice the frequency difference between the NRZ signal and the reference signal. A further disadvantage is the high latency of the slip pulses, which are shifted by about 90 degrees with respect to the frequency difference between the NRZ signal and the reference signal, which necessitates disabling the frequency-locked loop when the reference signal is locked.
Accordingly, a need exists for a frequency difference detector that provides output pulses with a high repetition rate and low latency and that need not include a phase shifter or a tub resistor.